The present invention relates to a nonvolatile semiconductor memory device and to a method for fabricating the same. At present, flash EEPROM (Electrically Erasable Programmable ROM) devices are used widely in electronic equipment as nonvolatile semiconductor memory devices which allow for electrical write and erase operations. The structures of memory cells in the nonvolatile semiconductor memory devices can be divided broadly into two types. The first one is a stacked-gate type having a multilayer electrode structure-composed of a floating gate electrode and a control gate electrode which are stacked successively on a semiconductor substrate. The second one is a split-gate type having an electrode structure composed of a floating gate electrode and a control gate electrode which are disposed adjacent to each other in opposing relation to a channel region in a semiconductor substrate.
Referring to the drawings, a description will be given herein below to a conventional split-gate nonvolatile semiconductor memory device.
FIG. 42 shows a cross-sectional structure of a split-gate nonvolatile semiconductor memory device disclosed in U.S. Pat. No. 5,780,341, which has a stepped portion formed in a portion of a semiconductor substrate underlying a floating gate electrode. As shown in FIG. 42, a main surface of a semiconductor substrate 201 composed of, e.g., p-type silicon is formed with a stepped portion 205 composed of a first surface region 202 serving as an upper stage, a second surface region 204 serving as a lower stage, and a step side region 204 connecting the upper and lower stages.
A control gate electrode 210 is formed on the first surface region 202 of the stepped portion 205 with a gate insulating film 211 interposed therebetween. A floating gate electrode 212 formed to cover up the stepped portion 205 is capacitively coupled to the side surface of the control gate electrode 210 closer to the stepped portion and opposed to the second surface region 203 with a silicon dioxide film 213 serving as a tunnel film interposed therebetween.
A heavily doped n-type source region 221 is formed in the first surface region 202 of the semiconductor substrate 201, while a lightly doped n-type drain region 222a is formed in an area of the second surface region 203 underlying the floating gate electrode 212 and a heavily doped drain region 222b is formed externally of the lightly doped drain region 222a. 
In an area of the first surface region 202 underlying the floating gate electrode 212, a p-type impurity region 223 containing a p-type impurity at a concentration higher than in the semiconductor substrate 201 is formed. In such a structure, the floating gate electrode 212 is positioned in the direction in which electrons that have been injected into the heavily source region 221 flow so that the efficiency with which channel electrons are injected is improved.
As a result of conducting various studies including simulation and the like, the present inventors have concluded that the conventional split-gate nonvolatile semiconductor memory device is unsatisfactory in terms of the effect of increasing the efficiency of electron injection which is exerted by the stepped portion 205 formed in the semiconductor substrate 201.
When an electric field is applied during a write operation, a high electric field is hard to propagate upwardly from the lower corner of the stepped portion 205 in the source-side end portion of the lightly doped drain region 222a so that the localization of the electric field is likely to occur only in the vicinity of the lower corner of the stepped portion 205. As a result, a region where the electric field is intensest deviates to a lower portion from the step side region 204 into which the channel electrons from the floating gate electrode 212 are intended to be actually injected. The channel electrons flow directly to the lightly doped drain region 222a through a region at a distance from the step side region 204. This prevents the channel electrons from being injected into the floating gate electrode 212 with a sufficiently high efficiency.
During an erase operation, the electrons accumulated in the floating gate electrode 212 are extracted as a FN tunnel current to the heavily doped drain region 222b through a tunnel film composed of the portion of the silicon dioxide film 213 opposed to the floating gate electrode 212. With the increasing miniaturization of the element, however, the area of the portion of the tunnel film which permits the passage of the electrons is reduced so that the erase operation becomes difficult.
For an easier erase operation, there is a method of enhancing the electric field applied to the tunnel film by increasing the drain voltage. In accordance with the method, however, holes having high energy (hot holes) generated in the heavily doped drain region 222b are generated simultaneously. The hot holes causes the problem that the reliability of the tunnel film is lowered or that the hot holes are captured in the tunnel film to degrade the characteristics of the element.
As the element is reduced in size, especially the gate length of the control gate electrode 210 is reduced, a short-channel effect, which is obscure in the conventional split-gate flash EEPROM device, is observed distinctly disadvantageously.